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High speed CML latch using active inductor in 0.18μm CMOS technology | Semantic Scholar
High speed CML latch using active inductor in 0.18μm CMOS technology | Semantic Scholar

Figure 4 from Low power inductor-less CML latch and frequency divider for full-rate 20 Gbps in 28-nm CMOS | Semantic Scholar
Figure 4 from Low power inductor-less CML latch and frequency divider for full-rate 20 Gbps in 28-nm CMOS | Semantic Scholar

Performance evaluation of the low-voltage CML D-latch topology - ScienceDirect
Performance evaluation of the low-voltage CML D-latch topology - ScienceDirect

ECEN620: Network Theory Broadband Circuit Design Fall 2022
ECEN620: Network Theory Broadband Circuit Design Fall 2022

A Novel Ultra High-Speed Flip-Flop-Based Frequency Divider: Ravindran Mohanavelu and Payam Heydari | PDF
A Novel Ultra High-Speed Flip-Flop-Based Frequency Divider: Ravindran Mohanavelu and Payam Heydari | PDF

KR100682266B1 - Differential output tspc d-type flip flop and frequency divider using it - Google Patents
KR100682266B1 - Differential output tspc d-type flip flop and frequency divider using it - Google Patents

An improved current mode logic latch for high‐speed applications - Kumawat - 2020 - International Journal of Communication Systems - Wiley Online Library
An improved current mode logic latch for high‐speed applications - Kumawat - 2020 - International Journal of Communication Systems - Wiley Online Library

Figure 1 from A 45 mW RTD/HBT MOBILE D-Flip Flop IC Operating up to 32 Gb/s | Semantic Scholar
Figure 1 from A 45 mW RTD/HBT MOBILE D-Flip Flop IC Operating up to 32 Gb/s | Semantic Scholar

4-bit Counter Using High-Speed Low-Voltage CML D-Flipflops | Semantic Scholar
4-bit Counter Using High-Speed Low-Voltage CML D-Flipflops | Semantic Scholar

Figure 1 from Design of low-power high-speed dual-modulus frequency divider with improved MOS current mode logic | Semantic Scholar
Figure 1 from Design of low-power high-speed dual-modulus frequency divider with improved MOS current mode logic | Semantic Scholar

An improved current mode logic latch for high‐speed applications
An improved current mode logic latch for high‐speed applications

Low Power Rail to Rail D Flip-Flop Using Current Mode Logic Structure
Low Power Rail to Rail D Flip-Flop Using Current Mode Logic Structure

DFF-based CMOS clock divider. | Download Scientific Diagram
DFF-based CMOS clock divider. | Download Scientific Diagram

Schematic timing diagram of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
Schematic timing diagram of the proposed NDR-based CML D flip-flop | Download Scientific Diagram

Electronics | Free Full-Text | A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
Electronics | Free Full-Text | A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS

PDF] New CML latch structure for high speed prescaler design | Semantic Scholar
PDF] New CML latch structure for high speed prescaler design | Semantic Scholar

Low Power Rail to Rail D Flip-Flop Using Current Mode Logic Structure
Low Power Rail to Rail D Flip-Flop Using Current Mode Logic Structure

Circuit configuration of the RTD/HBT MOBILE-based NRZ D-flip flop. | Download Scientific Diagram
Circuit configuration of the RTD/HBT MOBILE-based NRZ D-flip flop. | Download Scientific Diagram

PPT - Advantages of Using CMOS PowerPoint Presentation, free download - ID:3409185
PPT - Advantages of Using CMOS PowerPoint Presentation, free download - ID:3409185

CML based DFF combined with NAND function used in 4/5 prescaler block | Download Scientific Diagram
CML based DFF combined with NAND function used in 4/5 prescaler block | Download Scientific Diagram

KR100969864B1 - Cml type d flip-flop and frequency divide-by-odd number using the same - Google Patents
KR100969864B1 - Cml type d flip-flop and frequency divide-by-odd number using the same - Google Patents

Analysis and Design of High-Speed CMOS Frequency Dividers
Analysis and Design of High-Speed CMOS Frequency Dividers

Figure 5.21 from Cmos Logic and Current Mode Logic 5.1 Introduction | Semantic Scholar
Figure 5.21 from Cmos Logic and Current Mode Logic 5.1 Introduction | Semantic Scholar

A Dynamic Current Mode D-Flipflop for High Speed Application | Semantic Scholar
A Dynamic Current Mode D-Flipflop for High Speed Application | Semantic Scholar

CML based DFF used in 4/5 prescaler block | Download Scientific Diagram
CML based DFF used in 4/5 prescaler block | Download Scientific Diagram

High Speed Digital Blocks
High Speed Digital Blocks